In integrated semiconductor memories on a semiconductor chip, for example DRAM (dynamic random access memory) semiconductor memories, voltage generators are generally used for generating internal operating voltages of the integrated semiconductor memory. Thus, a stabilized internal operating voltage is generated from a supply voltage fed externally to the integrated semiconductor memory. Further operating voltages are derived from the stabilized internal operating voltage. In the case of a DRAM semiconductor memory, they are for example voltages which are used for turning on and turning off selection transistors of a memory cell array. The derived operating voltages are fed from the voltage generators via interconnects to circuit components of the semiconductor memory, such as, for example, a memory bank or the word lines or selection transistors of the memory bank.
However, voltage fluctuations may occur along the interconnects of such devices due to the design, fabrication (e.g., mask and lithography processes), and operation of the semiconductor chip. Thus, by way of example, fluctuations within the technology processes lead to location-dependent voltage fluctuations on a semiconductor chip. Decreasing feature sizes result in capacitive coupling effects between spatially closely arranged interconnects, which likewise bring about voltage fluctuations along an interconnect. Consequently, operating voltages that are generated by the same voltage generator have level fluctuations in an internal voltage network into which they are fed by the voltage generator. The level fluctuations of voltages occur both within a single memory bank and between different memory banks into which the voltages are fed. These fluctuations usually occur at some distance from the voltage generator that generates them, for example at the end of an interconnect. Since the transistor operating points, for example the operating points of selection transistors within a memory bank, are designed only for small voltage ranges, even small changes in the voltages across the chip have a great impact on the functionality. As a result, clusters of errors occur at specific places in the semiconductor chip. These errors may be eliminated for example after improving connecting lines.
In the case of so-called pico-probing, the voltage at a location on an interconnect is tapped off by fine contact needles of a measuring system. With this type of measurement, however, many errors can corrupt the result of the measurement. Moreover, the fine positioning and alignment of the contact needles on an interconnect is generally associated with a very great expenditure of time. Greater statistics with which measurement errors can be delimited cannot be achieved on account of the time-consuming measurement method. Furthermore, the pico-probing method can be employed only at the wafer level on specific analysis test systems, since it is only here that direct contact can be made with interconnects. At the packaged device, by contrast, there is currently no possibility of measuring voltages that have been generated by a voltage generator at a central location of the integrated semiconductor memory, such as the spine, for example, on interconnects at different places in the chip.